In static random access memories (SRAMs) it has been found desirable to equilibrate, the bit lines in response to an address transition. In SRAMs which use address transition detection (ATD), it has been deemed unnecessary to equilibrate when only a column address change has occurred. If only a column address change occurs, the word line which is selected will remain selected. Consequently, the cells which were selected remain selected so that the bit lines need not change because the selected cell has already differentiated the bit lines in the desired manner.
The problem that arose was that called "walk-down" on the bit lines for consecutive column only address transitions. The reason was that of not sufficiently precharging the data lines (also known as bit sense common lines) prior to the next column access. Between column accesses the column decoder must be turned off, followed by the the data lines being equilibrated (equalized and precharged), and then followed by the next column decoder being enabled. Under rapid column only changes it is difficult to get the data lines to the full voltage desired without sacrificing speed. The effect was to cause the high voltage side of the bit lines to lose voltage due to the coupling to the reduced voltage data lines.
Equilibrating the bit lines on a column only address change created a problem of comprising the data in the accessed cells, particularly in relatively weak cells, by reducing the high voltage side. This could be cured by disabling the word lines during a column only address change. This approach lost the advantage associated with retaining the same word line in an active state for a column only change.